A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An Improved Power Macro-Model for Arithmetic Datapath Components
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Proceedings of the 2003 international symposium on Low power electronics and design
Binding, Allocation and Floorplanning in Low Power High-Level Synthesis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Technology exploration for adaptive power and frequency scaling in 90nm CMOS
Proceedings of the 2004 international symposium on Low power electronics and design
Challenges and design choices in nanoscale CMOS
ACM Journal on Emerging Technologies in Computing Systems (JETC)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Modelling the impact of high level leakage optimization techniques on the delay of RT-components
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Variability-aware architecture level optimization techniques for robust nanoscale chip design
Computers and Electrical Engineering
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Using our framework supporting simultaneous behavioral to RTL synthesis, component-wise floorplanning, as well as ABB (adaptive body biasing) and VDD aware power and delay prediction, we present a performance neutral methodology for optimal VDD-island generation and multiple ABB application. We show that tuning supply and body voltage for the entire design reduces the total energy dissipation by 4.6-38.1% without any performance loss. By allowing more than one body voltage and without optimizing the floorplan, the savings do not rise any further. Carefully floorplanning the design, we can additionally use VDD-islands reducing the power by 8.7-49.2%. In addition to the power savings, the power and delay variability due to PTV (process, temperature, voltage) variation can be reduced with all proposed ABB approaches, assuming that only the chip structure has to be fixed at design time, but the voltage levels can be adapted after the system manufacturing.