Architectural power analysis: the dual bit type method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-level synthesis techniques for reducing the activity of functional units
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Scheduling and resource binding for low power
ISSS '95 Proceedings of the 8th international symposium on System synthesis
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
A new parameterizable power macro-model for datapath components
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Parameterized RTL power models for combinational soft macros
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Automatic nonlinear memory power modelling
Proceedings of the conference on Design, automation and test in Europe
Power Macro-Modelling for Firm-Macro
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Voltage- and ABB-island optimization in high level synthesis
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Analytical High-Level Power Model for LUT-Based Components
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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We propose an improved power macro-model for arithmetic datapath components, which is based on spatio-temporal correlations of two consecutive input vectors and the output vector. Based on the enhanced Hamming-distance model [3], we introduce an additional spatial distance for the input vector and the Hamming-distance of the output vector to improve model accuracy significantly. Experimental results show that the models standard deviation is reduced by 3% for small components and up to 23% for complex components. Because of its fast and accurate power prediction, this model can be used for fast high-level power analysis.