Memory modeling for system synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
System level optimization and design space exploration for low power
Proceedings of the 14th international symposium on Systems synthesis
Memory power models for multilevel power estimation and optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Improved Power Macro-Model for Arithmetic Datapath Components
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Predictable design of low power systems by pre-implementation estimation and optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
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