Architectural power analysis: the dual bit type method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power macromodeling for high level power estimation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Automatic characterization and modeling of power consumption in static RAMs
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
IEEE Transactions on Computers
A new parameterizable power macro-model for datapath components
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Memory modeling for system synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Automatic nonlinear memory power modelling
Proceedings of the conference on Design, automation and test in Europe
Estimation of lower and upper bounds on the power consumption from scheduled data flow graphs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Lookup Table Power Macro-Models for Behavioral Library Components
VOLTA '99 Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
An Efficient Approach with Scaling Capability to Improve Existing Memory Power Model
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
MODEST: a model for energy estimation under spatio-temporal variability
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Efficient algorithms for multilevel power estimation of VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A scalable power modeling approach for embedded memory using LIB format
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Hi-index | 0.00 |
Storage cost is a major factor in the total power consumption of digital signal processing circuits. Power models for on-chip memories are consequently an important ingredient in power aware design flows for estimation and optimization. Unfortunately, exact memory-modeling techniques are not widely applied in practice. This is mainly due to the vendors' need for intellectual property (IP) protection, the ill fit into vendors' design cycles and the significant overhead in time and manpower involved. To bridge the gap between vendors and designers, we suggest an automatic black box modeling approach. It is based on nonlinear regression that combines all desired properties: accuracy, flexibility, speed, low overhead, a good fit into the vendors' design cycle, IP protection, plus a mathematical form that is well suited for optimization.