PASTEL: a parameterized memory characterization system
Proceedings of the conference on Design, automation and test in Europe
Memory modeling for system synthesis
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Memory power models for multilevel power estimation and optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power Macromodeling for a High Quality RT-Level Power Estimation
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Power emulation: a new paradigm for power estimation
Proceedings of the 42nd annual Design Automation Conference
Cache coherence tradeoffs in shared-memory MPSoCs
ACM Transactions on Embedded Computing Systems (TECS)
Power macromodeling of MPSoC message passing primitives
ACM Transactions on Embedded Computing Systems (TECS) - Special Section LCTES'05
An Efficient Approach with Scaling Capability to Improve Existing Memory Power Model
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
MODEST: a model for energy estimation under spatio-temporal variability
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
A scalable power modeling approach for embedded memory using LIB format
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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An automatic modeling technique is presented in this paper that allows to build an accurate model of power consumption in embedded memory blocks. A software neural-network is used to create a regression tree by automatically splitting those variables that have a discontinuous effect on the power consumption. An application of the methodology to the modeling of a 0.35µm CMOS embedded SRAM is presented.