The design and implementation of PowerMill
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
The Designer's Guide to Spice and Spectre
The Designer's Guide to Spice and Spectre
Asymptotic Waveform Evaluation and Moment Matching for Interconnect Analysis
Asymptotic Waveform Evaluation and Moment Matching for Interconnect Analysis
A modeling and circuit reduction methodology for circuit simulation of DRAM circuits
MTDT '95 Proceedings of the 1995 IEEE International Workshop on Memory Technology, Design and Testing
Automatic characterization and modeling of power consumption in static RAMs
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Memory modeling for system synthesis
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
A power reduction technique with object code merging for application specific embedded processors
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Low-energy off-chip SDRAM memory systems for embedded applications
ACM Transactions on Embedded Computing Systems (TECS)
IDAP: A Tool for High Level Power Estimation of Custom Array Structures
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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PASTEL is a parameterized memory characterization system which extracts the characteristics of ASIC on-chip-memories such as delay, timing and power consumption which are important in LSI logic design. PASTEL is a fully-automated process from exact wire-RC extraction through circuit reduction, input vector generation, waveform measurement, data-sheet and library creation. The circuit reduction scheme can reduce the circuit simulation time by 2 order of magnitude while maintaining delay error within 100pSec of exact simulation.