Asymptotic Waveform Evaluation and Moment Matching for Interconnect Analysis

Efficient linear circuit analysis by Pade´ approximation via the Lanczos process

EURO-DAC '94 Proceedings of the conference on European design automation

Addressing high frequency effects in VLSI interconnects with full wave model and CFH

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

An efficient approach for moment-matching simulation of linear subnetworks with measured or tabulated data

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

A behavioral signal path modeling methodology for qualitative insight in and efficient sizing of CMOS opamps

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Reduced-order modelling of linear time-varying systems

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

PASTEL: a parameterized memory characterization system

Proceedings of the conference on Design, automation and test in Europe

Substrate crosstalk analysis in mixed signal CMOS integrated circuits: embedded tutorial

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference

Reduced Order Modeling for RLC Interconnect Tree Using Hurwitz Polynomial

Analog Integrated Circuits and Signal Processing

An efficient DC-gain matched balanced truncation realization for VLSI Interconnect circuit order reduction

Microelectronic Engineering

Krylov subspace techniques for reduced-order modeling of large-scale dynamical systems

Applied Numerical Mathematics

Interconnect Geometry Optimization Using Modular Artificial Neural Networks

Analog Integrated Circuits and Signal Processing

Signal Delay in Coupled, Distributed RC Lines in the Presence of Temporal Proximity

ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)

Wire Length and Width Bound Generation for High-Speed MCM and PCB Designs

MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference

Design and verification of high-speed VLSI physical design

Journal of Computer Science and Technology

Numerical Simulation and Modelling of Electronic and Biochemical Systems

Foundations and Trends in Electronic Design Automation

Manifold construction and parameterization for nonlinear manifold-based model reduction

Proceedings of the 2010 Asia and South Pacific Design Automation Conference

Survey and Evaluation of Automated Model Generation Techniques for High Level Modeling and High Level Fault Modeling

Journal of Electronic Testing: Theory and Applications