An efficient DC-gain matched balanced truncation realization for VLSI Interconnect circuit order reduction

Authors:
Xuan Zeng;Dian Zhou;Wei Cai
Affiliations:
ASIC & System State-Key-Lab, Microelectronic Department, Fudan University, Shanghai 200433, PR China;E. E. Department, University of Texas at Dallas Richardson, TX;E. E. Department, University of North Carolina at Charlotte, Charlotte, NC
Venue:
Microelectronic Engineering
Year:
2002

Citing 14
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Abstract

In this paper, we present a linear time DC-Gain matched BTR (DBTR) method for the VLSI interconnect order reduction. From the circuit point of view, the original BTR has a serious drawback that the DC gain between the original and the reduced order system doesn't match. We propose the DBTR method which can both match the DC gain and guarantee the performance of the reduced order system. Moreover, considering that the practical VLSI circuit order can be up to several thousands, we derive a linear time algorithm for computing a DBTR by extending the O(n) Krylov Subspace Oblique Projection. With linear time algorithm, the obstacle caused by the expensive computation cost of TBR for large circuit order reduction can be solved efficiently, and the advantage of the BTR, guaranteed performance on the reduced order system, can be fully utilized.