RICE: Rapid interconnect circuit evaluator
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
On the stability of moment-matching approximations in asymptotic waveform evaluation
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Fast approximation of the transient response of Lossy Transmision Line Trees
DAC '93 Proceedings of the 30th international Design Automation Conference
Stable and efficient reduction of substrate model networks using congruence transforms
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
An explicit RC-circuit delay approximation based on the first three moments of the impulse response
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Reduced-order modeling of large passive linear circuits by means of the SYPVL algorithm
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
PRIMA: passive reduced-order interconnect macromodeling algorithm
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
PRIMO: probability interpretation of moments for delay calculation
DAC '98 Proceedings of the 35th annual Design Automation Conference
h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Multipoint moment matching model for multiport distributed interconnect networks
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Buffer insertion with accurate gate and interconnect delay computation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Equivalent Elmore delay for RLC trees
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
TICER: realizable reduction of extracted RC circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Realizable reduction for RC interconnect circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
RLC interconnect delay estimation via moments of amplitude and phase response
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Polynomials and Linear Control Systems
Polynomials and Linear Control Systems
Asymptotic Waveform Evaluation and Moment Matching for Interconnect Analysis
Asymptotic Waveform Evaluation and Moment Matching for Interconnect Analysis
Hurwitz stable reduced order modeling for RLC interconnect trees
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
S2P: A Stable 2-Pole RC Delay and Coupling Noise Metric
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
An analytical delay model for RLC interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A delay model for interconnect trees based on ABCD matrix
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
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We investigate on-chip RLC interconnect reduced order modeling problem. A provably realizable and stable model order reduction approach is proposed. To guarantee stability of reduced order circuits, we first employ a realizable reduction for load approximation to preserve the first three driving-point admittance coefficients. Then, we use Hurwitz polynomials to approximate the denominators of original rational transfer functions. We prove that stability can be guaranteed during a hierarchical analysis while circuit response moments can still be matched implicitly. We also give some experimental results to show the accuracy and efficiency of the proposed approach.