Numerical recipes in C (2nd ed.): the art of scientific computing
Numerical recipes in C (2nd ed.): the art of scientific computing
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Stable and efficient reduction of substrate model networks using congruence transforms
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
An explicit RC-circuit delay approximation based on the first three moments of the impulse response
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Analytical delay models for VLSI interconnects under ramp input
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
PRIMA: passive reduced-order interconnect macromodeling algorithm
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Timing metrics for physical design of deep submicron technologies
ISPD '98 Proceedings of the 1998 international symposium on Physical design
h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A two moment RC delay metric for performance optimization
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Predicting coupled noise in RC circuits by matching 1, 2, and 3 moments
Proceedings of the 37th Annual Design Automation Conference
RLC interconnect delay estimation via moments of amplitude and phase response
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
An interconnect topology optimization by a tree transformation
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
A statistical static timing analysis considering correlations between delays
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Estimation of power distribution in VLSI interconnects
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Fast and accurate wire delay estimation for physical synthesis of large ASICs
Proceedings of the 12th ACM Great Lakes symposium on VLSI
PERI: a technique for extending delay and slew metrics to ramp inputs
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Reduced Order Modeling for RLC Interconnect Tree Using Hurwitz Polynomial
Analog Integrated Circuits and Signal Processing
An "effective" capacitance based delay metric for RC interconnect
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Closed form expressions for extending step delay and slew metrics to ramp inputs
Proceedings of the 2003 international symposium on Physical design
A delay metric for RC circuits based on the Weibull distribution
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Delay and slew metrics using the lognormal distribution
Proceedings of the 40th annual Design Automation Conference
Simple metrics for slew rate of RC circuits based on two circuit moments
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Analytic Modeling of Interconnects for Deep Sub-Micron Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Fitted Elmore delay: a simple and accurate interconnect delay model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interconnect Delay and Slew Metrics Using the First Three Moments
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Stochastic analysis of interconnect performance in the presence of process variations
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Robust analytical gate delay modeling for low voltage circuits
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Variational Interconnect Delay Metrics for Statistical Timing Analysis
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
An accurate slew metric for on-chip VLSI interconnect using Weibull distribution function
Proceedings of the International Conference on Advances in Computing, Communication and Control
Interconnect delay and slew metrics using the beta distribution
Proceedings of the Conference on Design, Automation and Test in Europe
Fast waveform estimation (FWE) for timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient delay metric on RC interconnects under saturated ramp inputs
ICCSA'06 Proceedings of the 2006 international conference on Computational Science and Its Applications - Volume Part IV
An improved Elmore delay model for VLSI interconnects
Mathematical and Computer Modelling: An International Journal
Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures
Proceedings of the 39th Annual International Symposium on Computer Architecture
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Moments of the impulse response are widely used for interconnect delay analysis, from the explicit Elmore delay (first moment of the impulse response) expression, to moment matching methods which create reduced order transimpedance and transfer function approximations. However, the Elmore delay is fast becoming ineffective for deep submicron technologies, and reduced order transfer function delays are impractical for use as early-phase design metrics or as design optimization cost functions. This paper describes an approach for fitting moments of the impulse response to probability density functions so that delays can be estimated from probability tables. For RC trees it is demonstrated that the incomplete gamma function provides a provably stable approximation. The step response delay is obtained from a one-dimensional table lookup.