TFA: a threshold-based filtering algorithm for propagation delay and slew calculation of high-speed VLSI interconnects

Authors:
S. Abbaspour;A. H. Ajami;M. Pedram;E. Tuncer
Affiliations:
University of Southern California, Los Angeles, CA;Magma Design Automation, Santa Clara, CA;University of Southern California, Los Angeles, CA;Magma Design Automation, Santa Clara, CA
Venue:
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Year:
2004

Citing 8
Cited 2

RICE: Rapid interconnect circuit evaluator

DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
PRIMO: probability interpretation of moments for delay calculation

DAC '98 Proceedings of the 35th annual Design Automation Conference
A two moment RC delay metric for performance optimization

ISPD '00 Proceedings of the 2000 international symposium on Physical design
An "effective" capacitance based delay metric for RC interconnect

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Buffer sizing for minimum energy-delay product by using an approximating polynomial

Proceedings of the 13th ACM Great Lakes symposium on VLSI
Improved Effective Capacitance Computations for Use in Logic and Layout Optimization

VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
The Elmore delay as a bound for RC trees with generalized input signals

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RC delay metrics for performance optimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp input

GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Fast waveform estimation (FWE) for timing analysis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper describes an efficient threshold-based filtering algorithm (TFA) for calculating the interconnect delay and slew (transition time) in high-speed VLSI circuits. The key idea is to divide the circuit nets into three groups of low, medium and high complexity nets, whereby for low and medium complexity nets either the first moment of the impulse response or the first and second moments are used. For the high-complexity nets, which are encountered infrequently, TFA resorts to the AWE method. The key contribution of the paper is to come up with very effective and efficient way of classifying the nets into these three groups. Experimental results show that on a large industrial circuit using a state-of-the-art commercial timing analysis that incorporates TFA, we were able to achieve delay and slew estimation accuracies that are quite comparable with the full-blown AWE-based calculators at runtimes that were only 14% higher than those of a simple Elmore-delay calculator.