PERI: a technique for extending delay and slew metrics to ramp inputs
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Closed form expressions for extending step delay and slew metrics to ramp inputs
Proceedings of the 2003 international symposium on Physical design
A delay metric for RC circuits based on the Weibull distribution
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Delay and slew metrics using the lognormal distribution
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Analytic Modeling of Interconnects for Deep Sub-Micron Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Interconnect Delay and Slew Metrics Using the First Three Moments
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Proceedings of the 2005 international symposium on Physical design
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Power optimal dual-Vdd buffered tree considering buffer stations and blockages
Proceedings of the 42nd annual Design Automation Conference
Robust analytical gate delay modeling for low voltage circuits
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Variational Interconnect Delay Metrics for Statistical Timing Analysis
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Non-gaussian statistical interconnect timing analysis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Practical variation-aware interconnect delay and slew analysis for statistical timing verification
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Digital Circuit Optimization via Geometric Programming
Operations Research
Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
An accurate slew metric for on-chip VLSI interconnect using Weibull distribution function
Proceedings of the International Conference on Advances in Computing, Communication and Control
Fast interconnect and gate timing analysis for performance optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast variational interconnect delay and slew computation using quadratic models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect delay and slew metrics using the beta distribution
Proceedings of the Conference on Design, Automation and Test in Europe
POMR: a power-aware interconnect optimization methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast waveform estimation (FWE) for timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient delay metric on RC interconnects under saturated ramp inputs
ICCSA'06 Proceedings of the 2006 international conference on Computational Science and Its Applications - Volume Part IV
TSV open defects in 3D integrated circuits: characterization, test, and optimal spare allocation
Proceedings of the 49th Annual Design Automation Conference
An improved Elmore delay model for VLSI interconnects
Mathematical and Computer Modelling: An International Journal
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For performance optimization tasks such as floorplanning, placement, buffer insertion, wire sizing, and global routing, the Elmore resistance-capacitance (RC) delay metric remains popular due to its simple closed form expression, fast computation speed, and fidelity with respect to simulation. More accurate delay computation methods are typically central processing unit intensive and/or difficult to implement. To bridge this gap between accuracy and efficiency/simplicity, we propose two new RC delay metrics called delay via two moments (D2M) and effective capacitance metric (ECM), which are virtually as simple and fast as the Elmore metric, but more accurate. D2M uses two moments of the impulse response in a simple formula that has high accuracy at the far end of RC lines. ECM captures resistive shielding effects by modeling the downstream capacitance by an “effective capacitance.” In contrast, the Elmore metric models this as a lumped capacitance, thereby ignoring resistive shielding. Although not as accurate as D2M, ECM yields consistent performance and may be well-suited to optimization due to its Elmore-like recursive construction