A gate-delay model for high-speed CMOS circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Reduced-order modeling of large linear subcircuits via a block Lanczos algorithm
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Stable and efficient reduction of substrate model networks using congruence transforms
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Efficient coupled noise estimation for on-chip interconnects
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
PRIMO: probability interpretation of moments for delay calculation
DAC '98 Proceedings of the 35th annual Design Automation Conference
h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
On switch factor based analysis of coupled RC interconnects
Proceedings of the 37th Annual Design Automation Conference
ClariNet: a noise analysis tool for deep submicron design
Proceedings of the 37th Annual Design Automation Conference
Towards true crosstalk noise analysis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Improved crosstalk modeling for noise constrained interconnect optimization
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Miller factor for gate-level coupling delay calculation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A delay metric for RC circuits based on the Weibull distribution
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A Method to Estimate Slew and Delay in Coupled Digital Circuits
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Noise Model for Multiple Segmented Coupled RC Interconnects
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Efficient Delay Calculation in Presence of Crosstalk
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Efficient Gate Delay Modeling for Large Interconnect Loads
MCMC '96 Proceedings of the 1996 IEEE Multi-Chip Module Conference (MCMC '96)
Poor Man's TBR: A Simple Model Reduction Scheme
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Fast bus waveform estimation at the presence of coupling noise
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Statistical waveform and current source based standard cell models for accurate timing analysis
Proceedings of the 45th annual Design Automation Conference
Current source based standard cell model for accurate signal integrity and timing analysis
Proceedings of the conference on Design, automation and test in Europe
Fast interconnect and gate timing analysis for performance optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Electronic Circuit & System Simulation Methods (SRE)
Electronic Circuit & System Simulation Methods (SRE)
Minimum crosstalk channel routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An analytical delay model for RLC interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RC delay metrics for performance optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
TETA: transistor-level waveform evaluation for timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Realizable reduction of interconnect circuits including self and mutual inductances
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Capacitive coupling noise in high-speed VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient linear circuit analysis by Pade approximation via the Lanczos process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper proposes a new technique, fast waveform estimation (FWE), to quickly and accurately estimate the output waveform for general resistance-capacitance (RC) interconnect networks in the presence of coupling noise. It is a common view that the traditional transient analysis is not feasible for full-chip timing analysis. The static methods suffer from inaccuracy and inability to capture the non-monotonic nature of signal waveform in the presence of coupling noise. The dynamic methods, such as, general model order reduction techniques provide a good compromise between the accuracy and efficiency. But they make no use of the typical topological structures of the general RC interconnect networks. The proposed FWE technique achieves a better overall performance through topological reduction of the general RC interconnect networks. It is demonstrated that the accuracy of the proposed method is comparable to the general model order reduction-based methods while maintaining an efficiency that is comparable to Elmore delay based analysis.