Efficient methods for large resistor networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast waveform estimation (FWE) for timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Reduction of an extracted netlist is an important preprocessing step for techniques such as model order reduction (MOR) in the design and analysis of very large scale integration circuits (VLSICs). This work describes a method for realizable reduction of extracted resistance-capacitance-inductance-mutual inductance netlists by node elimination. The method is much faster than MOR techniques and, hence, is appropriate as a preprocessing step. The proposed method eliminates nodes with time constants below a user-specified time constant. By giving the freedom to the user to select a critical point in the spectrum of nodal time constants, this method provides an option to make a tradeoff between accuracy and reduction. The proposed method preserves the dc characteristics and the first two moments at all nodes. It also recognizes and eliminates all the redundant inductances generated by the extraction tools. The proposed method naturally reduces to TICER (Sheehan, 1999) in the absence of any inductances.