Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
RICE: Rapid interconnect circuit evaluator
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
RC interconnect synthesis—a moment fitting approach
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
VLSI on-chip interconnection performance simulations and measurements
IBM Journal of Research and Development
The Elmore delay as bound for RC trees with generalized input signals
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Simultaneous gate and interconnect sizing for circuit-level delay optimization
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Clock distribution design and verification for PowerPC microprocessors
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A sequential quadratic programming approach to concurrent gate and wire sizing
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Coping with RC(L) interconnect design headaches
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Calculating worst-case gate delays due to dominant capacitance coupling
DAC '97 Proceedings of the 34th annual Design Automation Conference
A fast and accurate technique to optimize characterization tables for logic synthesis
DAC '97 Proceedings of the 34th annual Design Automation Conference
Accurate and efficient macromodel of submicron digital standard cells
DAC '97 Proceedings of the 34th annual Design Automation Conference
Timing metrics for physical design of deep submicron technologies
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Proposal of a timing model for CMOS logic gates driving a CRC &pgr; load
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Power estimation for a submicron CMOS inverter driving a CRC interconnect load
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Critical path analysis using a dynamically bounded delay model
Proceedings of the 37th Annual Design Automation Conference
Timing analysis and optimization of a high-performance CMOS processor chipset
Proceedings of the conference on Design, automation and test in Europe
Determination of worst-case crosstalk noise for non-switching victims in GHz+ buses
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Explicit gate delay model for timing evaluation
Proceedings of the 2003 international symposium on Physical design
Temporal Properties of Self-Timed Rings
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Shielding effect of on-chip interconnect inductance
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Blade and razor: cell and interconnect delay analysis using current-based models
Proceedings of the 40th annual Design Automation Conference
Analytical Fast Timing Simulation of MOS Circuits Driving RC Interconnects
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Crosstalk Aware Static Timing Analysis: A Two Step Approach
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Buffer delay change in the presence of power and ground noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
IR Drop and Ground Bounce Awareness Timing Model
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
A Waveform Independent Gate Model for Accurate Timing Analysis
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Determination of worst-case crosstalk noise for non-switching victims in GHz+ interconnects
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Constructing Current-Based Gate Models Based on Existing Timing Library
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Combinatorial algorithms for fast clock mesh optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load
Integration, the VLSI Journal
Silicon speedpath measurement and feedback into EDA flows
Proceedings of the 44th annual Design Automation Conference
A robust finite-point based gate model considering process variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A methodology for timing model characterization for statistical static timing analysis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Fast bus waveform estimation at the presence of coupling noise
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Characterizing multistage nonlinear drivers and variability for accurate timing and noise analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Worst-case aggressor-victim alignment with current-source driver models
Proceedings of the 46th Annual Design Automation Conference
Combinatorial algorithms for fast clock mesh optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast waveform estimation (FWE) for timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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