Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
On the general false path problem in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Analysis and design of latch-controlled synchronous digital circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A gate-delay model for high-speed CMOS circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Calculating worst-case gate delays due to dominant capacitance coupling
DAC '97 Proceedings of the 34th annual Design Automation Conference
PRIMA: passive reduced-order interconnect macromodeling algorithm
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Global harmony: coupled noise analysis for full-chip RC interconnect networks
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
False coupling interactions in static timing analysis
Proceedings of the 38th annual Design Automation Conference
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique
Proceedings of the 38th annual Design Automation Conference
Clock schedule verification with crosstalk
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Minimum delay optimization for domino logic circuits---a coupling-aware approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
RESTA: a robust and extendable symbolic timing analysis tool
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Timing Verification with Crosstalk for Transparently Latched Circuits
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Timing macro-modeling of IP blocks with crosstalk
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Trade-off between latch and flop for min-period sequential circuit designs with crosstalk
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Identification of delay measurable PDFs using linear dependency relationships
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper focuses on static timing analysis in the presence of capacitive coupling. We propose a novel gate delay model, the dynamically bounded delay model. In contrast to the min-max or bounded delay model which assumes a fixed delay range, [dmin, dmax], for each circuit component, our new model allows for the specification of delay variations and the conditions upon which the variations will hold. Novel static timing analysis algorithms can thus dynamically bound the delays. To demonstrate the effectiveness of this model and approach, we use our model to perform critical path analysis in the presence of capacitive coupling. Our experiments show that our approach avoids pessimism when compared to PERT analysis assuming worst case capacitive coupling.