Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications

Delay fault models and test generation for random logic sequential circuits

DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference

Certified timing verification and the transition delay of a logic circuit

DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference

Timing optimization by gate resizing and critical path identification

DAC '93 Proceedings of the 30th international Design Automation Conference

Timing uncertainty analysis for time-of-flight systems

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

The minimization and decomposition of interface state machines

DAC '94 Proceedings of the 31st annual Design Automation Conference

Gate-level timing verification using waveform narrowing

EURO-DAC '94 Proceedings of the conference on European design automation

Hierarchical timing analysis using conditional delays

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Timing analysis with known false sub graphs

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

BooleDozer: logic synthesis for ASICs

IBM Journal of Research and Development

A systematic technique for verifying critical path delays in a 300MHz Alpha CPU design using circuit simulation

DAC '96 Proceedings of the 33rd annual Design Automation Conference

An approximate timing analysis method for datapath circuits

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Efficient verification of determinate speed-independent circuits

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

Analysis of cyclic combinational circuits

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

Event propagation conditions in circuit delay computation

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Exact required time analysis via false path detection

DAC '97 Proceedings of the 34th annual Design Automation Conference

Approximate timing analysis of combinational circuits under the XBD0 model

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Hierarchical functional timing analysis

DAC '98 Proceedings of the 35th annual Design Automation Conference

Full-chip verification of UDSM designs

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

False loops through resource sharing

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

Exploiting multi-cycle false paths in the performance optimization of sequential circuits

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

Functional timing analysis for IP characterization

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting

IEEE Transactions on Computers

Critical path analysis using a dynamically bounded delay model

Proceedings of the 37th Annual Design Automation Conference

Timing Analysis of Combinational Circuits in Intuitionistic Propositional Logic

Formal Methods in System Design

Path verification using Boolean satisfiability

Proceedings of the conference on Design, automation and test in Europe

An advanced timing characterization method using mode dependecy

Proceedings of the 38th annual Design Automation Conference

Satisfiability models and algorithms for circuit delay computation

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Static timing analysis

Logic Synthesis and Verification

Post-layout optimization of power and timing for ECL LSIs

EDTC '95 Proceedings of the 1995 European conference on Design and Test

Elimination of multi-cycle false paths by state encoding

EDTC '95 Proceedings of the 1995 European conference on Design and Test

Deadline Analysis of Interrupt-Driven Software

IEEE Transactions on Software Engineering

Delay Fault Diagnosis for Non-Robust Test

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design

An efficient mechanism for performance optimization of variable-latency designs

Proceedings of the 44th annual Design Automation Conference

Efficient Boolean characteristic function for timed automatic test pattern generation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Variable-latency design by function speculation

Proceedings of the Conference on Design, Automation and Test in Europe

Certified timing verification and the transition delay of a logic circuit

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Functional timing analysis made fast and general

Proceedings of the 49th Annual Design Automation Conference

Small-delay-fault ATPG with waveform accuracy

Proceedings of the International Conference on Computer-Aided Design

Automatic test pattern generation for delay defects using timed characteristic functions

Proceedings of the International Conference on Computer-Aided Design

Sensitization criterion for threshold logic circuits and its application

Proceedings of the International Conference on Computer-Aided Design