Effects of delay models on peak power estimation of VLSI sequential circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications
Testing of Digital Systems
Accurate timing analysis using SAT and pattern-dependent delay models
Proceedings of the conference on Design, automation and test in Europe
A Simulator of Small-Delay Faults Caused by Resistive-Open Defects
ETS '08 Proceedings of the 2008 13th European Test Symposium
Effective and Efficient Test Pattern Generation for Small Delay Defect
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
Efficient Boolean characteristic function for timed automatic test pattern generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Incremental preprocessing methods for use in BMC
Formal Methods in System Design
Efficient SAT-Based Search for Longest Sensitisable Paths
ATS '11 Proceedings of the 2011 Asian Test Symposium
Effective preprocessing in SAT through variable and clause elimination
SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing
On the fault coverage of gate delay fault detecting tests
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Primitive delay faults: identification, testing, and design for testability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test pattern generation using Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Two new techniques for unit-delay compiled simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improved SAT-based ATPG: more constraints, better compaction
Proceedings of the International Conference on Computer-Aided Design
Automatic test pattern generation for delay defects using timed characteristic functions
Proceedings of the International Conference on Computer-Aided Design
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The detection of small-delay faults is traditionally performed by sensitizing transitions on a path of sufficient length from an input to an output of the circuit going through the fault site. While this approach allows efficient test generation algorithms, it may result in false positives and false negatives as well, i.e. undetected faults are classified as detected or detectable faults are classified as undetectable. We present an automatic test pattern generation algorithm which considers waveforms and their propagation on each relevant line of the circuit. The model incorporates individual delays for each gate and filtering of small glitches. The algorithm is based on an optimized encoding of the test generation problem by a Boolean satisfiability (SAT) instance and is implemented in the tool WaveSAT. Experimental results for ISCAS-85, ITC-99 and industrial circuits show that no known definition of path sensitization can eliminate false positives and false negatives at the same time, thus resulting in inadequate small-delay fault detection. WaveSAT generates a test if the fault is testable and is also capable of automatically generating a formal redundancy proof for undetectable small-delay faults; to the best of our knowledge this is the first such algorithm that is both scalable and complete.