Effects of delay models on peak power estimation of VLSI sequential circuits

Authors:
Michael S. Hsiao;Elizabeth M. Rudnick;Janak H. Patel
Affiliations:
Department of Electrical and Computer Engineering, Rutgers University, Piscataway, NJ;Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL;Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
Venue:
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Year:
1997

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Abstract

Previous work has shown that maximum switching density at a given node is extremely sensitive to a slight change in the delay at that node. However, when estimating the peak power for the entire circuit, the powers estimated must not be as sensitive to a slight variation or inaccuracy in the assumed gate delays because computing the exact gate delays for every gate in the circuit during simulation is expensive. Thus, we would like to use the simplest delay model possible to reduce the execution time for estimating power, while making sure that it provides an accurate estimate, i.e., that the peak powers estimated will not vary due to a variation in the gate delays. Results for four delay models are reported for the ISCAS85 combinational benchmark circuits, ISCAS89 sequential benchmark circuits, and several synthesized circuits.