Estimation of average switching activity in combinational and sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Computing the maximum power cycles of a sequential circuit
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Extreme delay sensitivity and the worst-case switching activity in VLSI circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Effects of delay models on peak power estimation of VLSI sequential circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Peak power estimation using genetic spot optimization for large VLSI circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Estimation of maximum power for sequential circuits considering spurious transitions
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Maximum power estimation for CMOS circuits using deterministic and statistical approaches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Estimation of average switching activity in combinational logic circuits using symbolic simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate-level power estimation using tagged probabilistic simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A satisfiability-based technique for symbolic modeling of event propagation in a circuit is presented in this paper which captures the events in the internal nodes of the circuit with a high level of detail. The model is used to accurately measure the peak single cycle transition power consumption in combinational and sequential circuits, which is closely affected by the switching activity in the circuit. Our technique is scalable, and adapts easily to ever increasing sizes of the custom cells (building blocks) in today's industry, without compromising on accuracy and correctness.