Extreme delay sensitivity and the worst-case switching activity in VLSI circuits

Feedback, correlation, and delay concerns in the power estimation of VLSI circuits

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Power estimation techniques for integrated circuits

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Hierarchical electromigration reliability diagnosis for VLSI interconnects

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Effects of delay models on peak power estimation of VLSI sequential circuits

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

A power optimization method considering glitch reduction by gate sizing

ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design

Peak power estimation using genetic spot optimization for large VLSI circuits

DATE '99 Proceedings of the conference on Design, automation and test in Europe

A practical gate resizing technique considering glitch reduction for low power design

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Least-square estimation of average power in digital CMOS circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model

EDTC '97 Proceedings of the 1997 European conference on Design and Test

A Test Vector Inhibiting Technique for Low Energy BIST Design

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

High-level macro-modeling and estimation techniques for switching activity and power consumption

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Power Estimation Under Uncertain Delays

Integrated Computer-Aided Engineering

Using SAT-based techniques in power estimation

Microelectronics Journal

Satisfiability models for maximum transition power

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Efficient algorithms for multilevel power estimation of VLSI circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems