Transition density, a stochastic measure of activity in digital circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
LP based cell selection with constraints of timing, area, and power consumption
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Extreme delay sensitivity and the worst-case switching activity in VLSI circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Power reduction by gate sizing with path-oriented slack calculation
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
An iterative gate sizing approach with accurate delay evaluation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Power vs. delay in gate sizing: conflicting objectives?
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Inaccuracies in power estimation during logic synthesis
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On average power dissipation and random pattern testability of CMOS combinational logic networks
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Gate sizing in MOS digital circuits with linear programming
EURO-DAC '90 Proceedings of the conference on European design automation
A practical gate resizing technique considering glitch reduction for low power design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
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We propose a power optimization method considering glitch reduction by gate sizing. Our method reduces not only the amount of capacitive and short-circuit power consumption but also the power dissipated by glitches which has not been exploited previously. In the optimization method, we improve the accuracy of statistical glitch estimation method and device a gate sizing algorithm that utilizes perturbations for escaping a bad local solution. The effect of our method is verified experimentally using 12 benchmark circuits with a 0.5 µm standard cell library. Gate sizing reduces the number of glitch transitions by 38.2 % on average and by 63.4 % maximum. This results in the reduction of total transitions by 12.8 % on average. When the circuits are optimized for power without delay constraints, the power dissipation is reduced by 7.4 % on average and by 15.7 % maximum further from the minimum-sized circuits.