DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A multiple clocking scheme for low power RTL design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
An iterative gate sizing approach with accurate delay evaluation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Power vs. delay in gate sizing: conflicting objectives?
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Integrated resynthesis for low power
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Power Optimization in VLSI Layout: A Survey
Journal of VLSI Signal Processing Systems
A power optimization method considering glitch reduction by gate sizing
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
A practical gate resizing technique considering glitch reduction for low power design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Power-delay optimizations in gate sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Transistor sizing of energy-delay--efficient circuits
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Low Power VLSI Design Techniques - The Current State
Integrated Computer-Aided Engineering
Soft error-aware power optimization using gate sizing
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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This paper presents a new LP based optimal cell selection method. Optimal cell selection is a useful tool for final tuning of LSI designs. It replaces drivabilities of cells, adjusting timing, area, and power constraints. Using the latest and earliest arrival times, it can handle both setup and hold time constraints. We also make an efficient initial basis, which speeds up a simplex LP solver by 5 times without any relaxations nor approximations. From experimental results, it reduces the clock cycle of a manual designed 13k-transistor chip by 17% without any increase of area.