A multiple clocking scheme for low power RTL design

Principles of CMOS VLSI design: a systems perspective

Principles of CMOS VLSI design: a systems perspective

SYNTEST: an environment for system-level design for test

EURO-DAC '92 Proceedings of the conference on European design automation

Re-encoding sequential circuits to reduce power dissipation

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Multi-level network optimization for low power

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

LP based cell selection with constraints of timing, area, and power consumption

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

On average power dissipation and random pattern testability of CMOS combinational logic networks

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

VLSI and Modern Signal Processing

VLSI and Modern Signal Processing

Saving Power in the Control Path of Embedded Processors

IEEE Design & Test

Saving Power by Synthesizing Gated Clocks for Sequential Circuits

IEEE Design & Test

Facet: A procedure for the automated synthesis of digital systems

DAC '83 Proceedings of the 20th Design Automation Conference

Optimizing power using transformations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems