Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Logic design principles with emphasis on testable semicustom circuits
Logic design principles with emphasis on testable semicustom circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Technology decomposition and mapping targeting low power dissipation
DAC '93 Proceedings of the 30th international Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Synthesis of Asynchronous State Machines Using A Local Clock
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
A multiple clocking scheme for low power RTL design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Glitch analysis and reduction in register transfer level power optimization
DAC '96 Proceedings of the 33rd annual Design Automation Conference
State assignment for FSM low power design
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Power management techniques for control-flow intensive designs
DAC '97 Proceedings of the 34th annual Design Automation Conference
High-level power modeling, estimation, and optimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
Kernel-based power optimization of RTL components: exact and approximate extraction algorithms
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Integrated test of interacting controllers and datapaths
ACM Transactions on Design Automation of Electronic Systems (TODAES)
At-Speed Logic BIST Using a Frozen Clock Testing Strategy
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Power-aware clock tree planning
Proceedings of the 2004 international symposium on Physical design
A high-level register optimization technique for minimizing leakage and dynamic power
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Proceedings of the conference on Design, automation and test in Europe
Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations
Transactions on High-Performance Embedded Architectures and Compilers I
Power optimization for application-specific networks-on-chips: A topology-based approach
Microprocessors & Microsystems
Power optimization with power islands synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Logic synthesis for low power using clock gating and rewiring
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Design of variable wordlength viterbi decoder in BICM-OFDM systems
ISCIT'09 Proceedings of the 9th international conference on Communications and information technologies
Sub-row sleep transistor insertion for concurrent clock-gating and power-gating
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Low-Power 32bit×32bit multiplier design with pipelined block-wise shutdown
HiPC'05 Proceedings of the 12th international conference on High Performance Computing
Variable wordlength soft-decision Viterbi decoder for power-efficient wireless LAN
Integration, the VLSI Journal
Efficient automated clock gating using codel
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Low-energy-transmission of data on submicron interconnects
WSEAS TRANSACTIONS on COMMUNICATIONS
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Portable devices demand low power consumption to prolong battery life. Gating the clock is one strategy for saving power. The authors' technique identifies self-loops in an FSM and uses the function described by the self-loops to gate the clock. Applying these techniques to standard benchmarks achieved an average 25% less power dissipation at a cost of only 5% more area.