IEEE Transactions on Computers
Test Length for Pseudorandom Testing
IEEE Transactions on Computers
Linear Feedback Shift Register Design Using Cyclic Codes
IEEE Transactions on Computers
From defects to failures: a view of dependable computing
ACM SIGARCH Computer Architecture News - Special Issue: Architectural Support for Operating Systems
IBM Journal of Research and Development
Testability of asynchronous timed control circuits with delay assumptions
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Boolean Matrix Transforms for the Minimization of Modulo-2 Canonical Expansions
IEEE Transactions on Computers
Detection and Location of Multiple Faults in Baseline Interconnection Networks
IEEE Transactions on Computers
ROM-based finite state machines with PLA address modifiers
EURO-DAC '92 Proceedings of the conference on European design automation
Automatic technology mapping for generalized fundamental-mode asynchronous designs
DAC '93 Proceedings of the 30th international Design Automation Conference
Optimization of combinational logic circuits based on compatible gates
DAC '93 Proceedings of the 30th international Design Automation Conference
On testing delay faults in macro-based combinational circuits
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Decomposition methods for library binding of speed-independent asynchronous designs
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
On synthesis-for-testability of combinational logic circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A Multiple-Sequence Generator Based on Inverted Nonlinear Autonomous Machines
IEEE Transactions on Computers
Counting Two-State Transition-Tour Sequences
IEEE Transactions on Computers
GigaHertz MUX-DEMUX Chip with HF BIST
Analog Integrated Circuits and Signal Processing - Special issue: selected articles from the 1995 NORCHIP seminar
The disjunctive decomposition of logic functions
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
An output encoding problem and a solution technique
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Predicate rewriting for translating Boolean queries in a heterogeneous information system
ACM Transactions on Information Systems (TOIS)
Stuck-at fault detection in parity trees
ACM '86 Proceedings of 1986 ACM Fall joint computer conference
Intermediacy Prediction for High Speed Berger Code Checkers
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Readings in hardware/software co-design
IEEE Design & Test
Saving Power by Synthesizing Gated Clocks for Sequential Circuits
IEEE Design & Test
Efficient Multiplexer Synthesis Techniques
IEEE Design & Test
IEEE Transactions on Computers
Notes on Multiple Input Signature Analysis
IEEE Transactions on Computers
IEEE Transactions on Computers
ICPP '97 Proceedings of the international Conference on Parallel Processing
Synthesis of multilevel fault-tolerant combinational circuits
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A row-based FPGA for single and multiple stuck-at fault detection
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Advanced Synchronous Scan Test Methodology for Multi Clock Domain ASICs
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
COMBINATIONAL LOGIC SYNTHESIS FOR DIVERSITY IN DUPLEX SYSTEMS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Technique For Testing A Very High Speed Mixed Signal Read Channel Design
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Oscillation and Sequential Behavior Caused by Interconnect Opens in Digital CMOS Circuits
ITC '97 Proceedings of the 1997 IEEE International Test Conference
SCAN SYNTHESIS FOR ONE-HOT SIGNALS
ITC '97 Proceedings of the 1997 IEEE International Test Conference
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Testing strategies for networks on chip
Networks on chip
Tools and devices supporting the pseudo-exhaustive test
EURO-DAC '90 Proceedings of the conference on European design automation
Response compaction with any number of unknowns using a new LFSR architecture
Proceedings of the 42nd annual Design Automation Conference
XPAND: An Efficient Test Stimulus Compression Technique
IEEE Transactions on Computers
High level equivalence symmetric input identification
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Meta-searches in peer-to-peer networks
Personal and Ubiquitous Computing
SAT-based ATPG using multilevel compatible don't-cares
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Problems of Information Transmission
Optimal polarity for dual Reed-Muller expressions
MINO'08 Proceedings of the 7th WSEAS International Conference on Microelectronics, Nanoelectronics, Optoelectronics
Minimization of OR-XNOR expressions using four new linking rules
AIKED'08 Proceedings of the 7th WSEAS International Conference on Artificial intelligence, knowledge engineering and data bases
Synthesis of multi-level dual reed-muller expressions
NANOTECHNOLOGY'09 Proceedings of the 1st WSEAS international conference on Nanotechnology
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Finding Efficient Circuits Using SAT-Solvers
SAT '09 Proceedings of the 12th International Conference on Theory and Applications of Satisfiability Testing
A combinatorial approach to X-tolerant compaction circuits
IEEE Transactions on Information Theory
Fast coding for dual Reed-Muller expressions
EDUCATION'09 Proceedings of the 6th WSEAS international conference on Engineering education
Hybrid design for testability combining scan and clock line control and method for test generation
ITC'94 Proceedings of the 1994 international conference on Test
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Digital testing theory and practice
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Reconfigurable hardware for Pseudo-exhaustive test
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Built-in test compiler in an ASIC environment
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
On the testing of multiplexers
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Exact minimization of dual Reed-Muller expansions
ACS'06 Proceedings of the 6th WSEAS international conference on Applied computer science
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology
Journal of Electronic Testing: Theory and Applications
Test data compression using interval broadcast scan for embedded cores
Microelectronics Journal
Novel Self-Timed, Pipelined Clock Scan Architecture
Journal of Electronic Testing: Theory and Applications
Overcoming post-silicon validation challenges through quick error detection (QED)
Proceedings of the Conference on Design, Automation and Test in Europe
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