Synthesis of multilevel fault-tolerant combinational circuits

Authors:
A. Bogliolo;M. Damiani
Affiliations:
D.E.I.S., University of Bologna, Bologna, I-40136;D.E.I., University of Padova, Padova, I-35131
Venue:
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Year:
1995

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Abstract

In this paper we present a new approach to the design of multilevel fault-tolerant circuits. The approach is based on introducing a minimal amount of fault-masking redundancy during a multilevel logic optimization, process. This is done by taking into account the degrees of freedom associated with internal don't care conditions. Experimental results obtained on several benchmark circuits compare very favourably with fault-tolerant implementations based on traditional gate-level strategies.