Fault tolerant and fault testable hardware design
Fault tolerant and fault testable hardware design
Fault-tolerant computing: theory and techniques; vol. 1
Fault-tolerant computing: theory and techniques; vol. 1
Graphs, Codes and Designs
A theory of fault-tolerant design for digital systems
A theory of fault-tolerant design for digital systems
Solutions to the Minimization Problem of Fault-Tolerant Logic Circuits
IEEE Transactions on Computers
Test patterns for fault-tolerant logic circuits using block design concepts
ACM-SE 30 Proceedings of the 30th annual Southeast regional conference
Testing of Fault-Tolerant Hardware Through Partial Control of Inputs
IEEE Transactions on Computers
Fault-tolerant systems with concurrent error-locating capability
Journal of Computer Science and Technology
Synthesis of multilevel fault-tolerant combinational circuits
EDTC '95 Proceedings of the 1995 European conference on Design and Test
14.2 Applying Built-In Self-Test to Majority Voting Fault Tolerant Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Complex Reliability Evaluation of Voters for Fault Tolerant Designs
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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The use of redundancy to attain a fault-tolerant system design is described. Specifically, a general theory of redundancy is proposed that allows the design of fault-tolerant structures at the system-level, gate-level, or both. The theory accounts for classic approaches to redundant design such as TMR, NMR, and quadded and interwoven logics. It is shown that, by using mathematical block theory, it is possible to describe complex interconnections of redundant elements in a simple, straightforward fashion. Comparisons are made with other approaches to redundant design.