Fault tolerant and fault testable hardware design
Fault tolerant and fault testable hardware design
A General Constructive Approach to Fault-Tolerant Design Using Redundancy
IEEE Transactions on Computers
Majority voting fault and defect tolerance in vary large scale and wafer scale integrated circuits
Majority voting fault and defect tolerance in vary large scale and wafer scale integrated circuits
Graphs, Codes and Designs
A theory of fault-tolerant design for digital systems
A theory of fault-tolerant design for digital systems
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Fault-tolerant logic circuits have been considered untestable due to the redundancy introduced into the logic circuits to mask faults. Recently, the block design concepts have been used to construct system and gate level fault-tolerant logic circuits and to find a minimal design. Conditions have been established to construct testable fault-tolerant circuits. This paper investigates the use of the block design concepts to generate test patterns for fault-tolerant logic circuits designed according to certain criteria. Algorithms are developed to construct fault-tolerant circuits and to generate minimal test patterns directly from the block design representation of the circuits.