Logic design principles with emphasis on testable semicustom circuits
Logic design principles with emphasis on testable semicustom circuits
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Parallel Signature Analysis Design with Bounds on Aliasing
IEEE Transactions on Computers
On output response compression in the presence of unknown output values
Proceedings of the 39th annual Design Automation Conference
OPMISR: the foundation for compressed ATPG vectors
Proceedings of the IEEE International Test Conference 2001
Multiple-output propagation transition fault test
Proceedings of the IEEE International Test Conference 2001
Analysis and Design of Optimal Combinational Compactors
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Stuck-Fault Tests vs. Actual Defects
ITC '00 Proceedings of the 2000 IEEE International Test Conference
X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Embedded Deterministic Test for Low-Cost Manufacturing Test
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Compacting Test Responses for Deeply Embedded SoC Cores
IEEE Design & Test
On Compacting Test Response Data Containing Unknown Values
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
ITC '04 Proceedings of the International Test Conference on International Test Conference
X-Masking During Logic BIST and Its Impact on Defect Coverage
ITC '04 Proceedings of the International Test Conference on International Test Conference
Channel Masking Synthesis for Efficient On-Chip Test Compression
ITC '04 Proceedings of the International Test Conference on International Test Conference
X-Tolerant Test Response Compaction
IEEE Design & Test
X-masking during logic BIST and its impact on defect coverage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 43rd annual Design Automation Conference
Test response compactor with programmable selector
Proceedings of the 43rd annual Design Automation Conference
Using reiterative LFSR based X-masking to increase output compression in presence of unknowns
Proceedings of the 18th ACM Great Lakes symposium on VLSI
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
On compaction utilizing inter and intra-correlation of unknown states
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fully X-tolerant, very high scan compression
Proceedings of the 47th Design Automation Conference
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This paper presents a new test response compaction technique with any number of unknown logic values (X's) in the test response bits. The technique leverages an X-tolerant response compactor (X-compact), and forces X's that are not tolerated by X-Compact to known values. The data required to designate the X's not tolerated by the X-compactor, also called mask data, is stored in a compressed format on the tester and decompressed on-chip. We applied this technique to four industrial designs and obtained 26-fold to 60-fold reduction in test response data volume with no or minimal impact on test quality.