Channel Masking Synthesis for Efficient On-Chip Test Compression

  • Authors:
  • Vivek Chickermane;Brian Foutz;Brion Keller

  • Affiliations:
  • Cadence Design Systems, Endicott, NY, USA;Cadence Design Systems, Endicott, NY, USA;Cadence Design Systems, Endicott, NY, USA

  • Venue:
  • ITC '04 Proceedings of the International Test Conference on International Test Conference
  • Year:
  • 2004

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Abstract

The effectiveness of on-product Test Compression methods is degraded by the capture of unknown logic states ("X-states") by the scan elements. This paper describes a simple but cost-effective solution called channel masking that masks the X-states and allows test compression methods to be widely deployed on a variety of designs. It also discusses various aspects of the channel masking hardware and the synthesis and validation methodology to support its use in a typical design flow. Results are presented to show its effectiveness on some large industrial designs.