Test volume and application time reduction through scan chain concealment
Proceedings of the 38th annual Design Automation Conference
On output response compression in the presence of unknown output values
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Extending OPMISR beyond 10x Scan Test Efficiency
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Response compaction with any number of unknowns using a new LFSR architecture
Proceedings of the 42nd annual Design Automation Conference
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X-Masking During Logic BIST and Its Impact on Defect Coverage
ITC '04 Proceedings of the International Test Conference on International Test Conference
Channel Masking Synthesis for Efficient On-Chip Test Compression
ITC '04 Proceedings of the International Test Conference on International Test Conference
X-compact: an efficient response compaction technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scan test planning for power reduction
Proceedings of the 44th annual Design Automation Conference
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The paper presents an efficient method for synthesis of scan chain selection logic. It is capable of acting as a flexible X-control logic for test response compactors. The same circuitry can also be employed to selectively gate scan chains for diagnostic purposes.