Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Test volume and application time reduction through scan chain concealment
Proceedings of the 38th annual Design Automation Conference
On output response compression in the presence of unknown output values
Proceedings of the 39th annual Design Automation Conference
Tailoring ATPG for embedded testing
Proceedings of the IEEE International Test Conference 2001
OPMISR: the foundation for compressed ATPG vectors
Proceedings of the IEEE International Test Conference 2001
Test vector encoding using partial LFSR reseeding
Proceedings of the IEEE International Test Conference 2001
Reducing Test Application Time for Full Scan Embedded Cores
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
4.2 Synthesis of Zero-Aliasing Elementary-Tree Space Compactors
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Packet-Based Input Test Data Compression Techniques
ITC '02 Proceedings of the 2002 IEEE International Test Conference
X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Embedded Deterministic Test for Low-Cost Manufacturing Test
ITC '02 Proceedings of the 2002 IEEE International Test Conference
On Test Data Volume Reduction for Multiple Scan Chain Designs
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Response compaction with any number of unknowns using a new LFSR architecture
Proceedings of the 42nd annual Design Automation Conference
ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Response shaper: a novel technique to enhance unknown tolerance for output response compaction
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Coverage loss by using space compactors in presence of unknown values
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the 43rd annual Design Automation Conference
Test response compactor with programmable selector
Proceedings of the 43rd annual Design Automation Conference
Unknown blocking scheme for low control data volume and high observability
Proceedings of the conference on Design, automation and test in Europe
A hybrid scheme for compacting test responses with unknown values
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
On compaction utilizing inter and intra-correlation of unknown states
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The design of a test response compactor called a Block Compactoris given. Block Compactors belong to a new class of compactorscalled Finite Memory Compactors. Different from spacecompactors, finite memory compactors contain memory elements.Also unlike time compactors, finite memory compactors havefinite impulse response. These properties give finite memorycompactors the ability to achieve higher compaction ratios thanspace compactors and still be able to tolerate unknown values intest responses. The proposed Block Compactors, as an instance offinite memory compactors generate a signature of response data inseveral scan cycles. Results presented on several industrial designsshow that Block Compactors provide better test quality and higherdata compaction than earlier works on test response compactors.