Programmable BIST Space Compactors
IEEE Transactions on Computers
Optimal Zero-Aliasing Space Compaction of Test Responses
IEEE Transactions on Computers
On output response compression in the presence of unknown output values
Proceedings of the 39th annual Design Automation Conference
Theory of Information and Coding
Theory of Information and Coding
Extending OPMISR beyond 10x Scan Test Efficiency
IEEE Design & Test
Design of compactors for signature-analyzers in built-in self-test
Proceedings of the IEEE International Test Conference 2001
Analysis and Design of Optimal Combinational Compactors
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Zero-Aliasing Space Compaction of Test Responses Using a Single Periodic Output
IEEE Transactions on Computers
On Compacting Test Response Data Containing Unknown Values
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
X-compact: an efficient response compaction technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 43rd annual Design Automation Conference
Study on Expansion of Convolutional Compactors over Galois Field
IEICE - Transactions on Information and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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This paper addresses the problem of test response compaction. In order to maximize compaction ratio, a single-output encoder based on check matrix of a (n, n-1, m, 3) convolutional code is proposed. Theoretic analysis for this encoder is presented to avoid two and any odd erroneous bit cancellations, handle one unknown bit(X bit) and diagnose one erroneous bit. The X-bits tolerance capacity can be enhanced by choosing a proper memory size and weight of check matrix, which can also be obtained by an optimized input assignment algorithm. The theoretic analysis and experimental results on aliasing shows the efficiency of the proposed encoder.