Proceedings of the 1st conference on Computing frontiers
On Compacting Test Response Data Containing Unknown Values
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Response compaction with any number of unknowns using a new LFSR architecture
Proceedings of the 42nd annual Design Automation Conference
Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Test response compactor with programmable selector
Proceedings of the 43rd annual Design Automation Conference
X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis
IEEE Design & Test
GECOM: test data compression combined with all unknown response masking
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Scan chain organization for embedded diagnosis
Proceedings of the conference on Design, automation and test in Europe
Study on Expansion of Convolutional Compactors over Galois Field
IEICE - Transactions on Information and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
On compaction utilizing inter and intra-correlation of unknown states
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fully X-tolerant, very high scan compression
Proceedings of the 47th Design Automation Conference
A combinatorial approach to X-tolerant compaction circuits
IEEE Transactions on Information Theory
BISD: scan-based built-in self-diagnosis
Proceedings of the Conference on Design, Automation and Test in Europe
A diagnosis algorithm for extreme space compaction
Proceedings of the Conference on Design, Automation and Test in Europe
Diagnosis of logic circuits using compressed deterministic data and on-chip response comparison
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test data compression using selective encoding of scan slices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Construction and Analysis of Augmented Time Compactors
Journal of Electronic Testing: Theory and Applications
Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs
Journal of Electronic Testing: Theory and Applications
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This paper addresses the problem of compacting test responsesin the presence of unknowns at the input of thecompactor by exploiting the capabilities of well-known errordetection and correction codes. The technique, calledi-Compact, uses Saluja-Karpovsky Space Compactors, butpermits detection and location of errors in the presence ofunknown logic (X) values with help from the ATE. The advantagesof i-Compact are: 1. Small number of output pinsfrom the compactors for a required error detection capability;2. Small tester memory for storing expected responses;3. Flexibility of choosing several different combinations ofnumber of X values and number of bit errors for error detectionwithout altering the hardware compactor; 4. Samehardware capable of identifying the line that produced anerror in presence of unknowns; 5. Use of non-proprietarycodes found in the literature of 1950s; and 6. Independentof the circuit and the test generator.