Multiple error detection and identification via signature analysis
Journal of Electronic Testing: Theory and Applications
Diagnosis of Scan Cells in BIST Environment
IEEE Transactions on Computers
Design of Self-Diagnostic Boards by Multiple Signature Analysis
IEEE Transactions on Computers
An Efficient Scheme to Diagnose Scan Chains
Proceedings of the IEEE International Test Conference
A technique for fault diagnosis of defects in scan chains
Proceedings of the IEEE International Test Conference 2001
A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Improving the efficiency of error identification via signature analysis
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Diagnosis of scan path failures
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Fault Diagnosis in Scan-Based BIST Using Both Time and Space Information
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
On compaction utilizing inter and intra-correlation of unknown states
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A diagnosis algorithm for extreme space compaction
Proceedings of the Conference on Design, Automation and Test in Europe
Identification of failing tests with cycling registers
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Diagnosis of Failing Scan Cells through Orthogonal Response Compaction
ETS '11 Proceedings of the 2011 Sixteenth IEEE European Test Symposium
Scan-based BIST fault diagnosis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
X-compact: an efficient response compaction technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Identification of error-capturing scan cells in scan-BIST with applications to system-on-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault Diagnosis With Convolutional Compactors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hi-index | 0.00 |
This paper presents a novel scheme to address the challenge of identifying failing scan cells from production test responses in the presence of scan compression. The scheme is based on a very simple test response compactor employing orthogonal--spatial and time--signatures. The advantage of this scheme as compared to previous work in this field is the simple and incremental nature of the compaction hardware required. The ability of the scheme to accurately identify failing scan cells from compacted responses has been measured on production fail data from five industrial designs and is reported herein.