Fault dictionary compaction by output sequence removal
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Diagnosis of Scan Cells in BIST Environment
IEEE Transactions on Computers
Improved fault diagnosis in scan-based BIST via superposition
Proceedings of the 37th Annual Design Automation Conference
Diagnosis for scan-based BIST: reaching deep into the signatures
Proceedings of the conference on Design, automation and test in Europe
Failure Diagnosis of Structured VLSI
IEEE Design & Test
Dynamic diagnosis of sequential circuits based on stuck-at faults
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Improving the efficiency of error identification via signature analysis
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Fault Diagnosis in Scan-Based BIST Using Both Time and Space Information
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Dynamic fault dictionaries and two-stage fault isolation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scan-based BIST fault diagnosis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Creating small fault dictionaries [logic circuit fault diagnosis]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Embedded fault diagnosis in digital systems with BIST
Microprocessors & Microsystems
Squashing microcode stores to size in embedded systems while delivering rapid microcode accesses
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs
Journal of Electronic Testing: Theory and Applications
| Hi-index | 14.98 |
Partitioning techniques enable identification of fault-embedding scan cells in scan-based BIST. We introduce, in this paper, deterministic partitioning techniques capable of resolving the location of the fault-embedding scan cells. We outline a complete mathematical analysis that identifies the class of deterministic partitioning structures and complement this rigorous mathematical analysis with an exposition of the appropriate cost-effective implementation techniques. We validate the superiority of the deterministic techniques both in an average-case sense by conducting simulation experiments and in a worst-case sense through a thorough mathematical analysis.