Proofs: a fast, memory efficient sequential circuit fault simulator
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
On the generation of small dictionaries for fault location
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Fault dictionary compression and equivalence class computation for sequential circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Fault Location with Current Monitoring
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
A fault list reduction approach for efficient bridge fault diagnosis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Compact Dictionaries for Fault Diagnosis in Scan-BIST
IEEE Transactions on Computers
An Efficient Dictionary Organization for Maximum Diagnosis
Journal of Electronic Testing: Theory and Applications
Design and analysis of compact dictionaries for diagnosis in scan-BIST
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents dynamic two-stage fault isolation for sequential random logic very large scale integrated (VLSI) circuits, and introduces limited and dynamic fault dictionaries. In the first stage of the dynamic process, a limited fault dictionary identifies candidate faults, which are further distinguished in the second stage by a dictionary generated dynamically for the candidate faults and a subset of the test vectors. This provides high resolution but avoids the costs of full static dictionaries. Two-stage fault isolation is evaluated for benchmark circuits and on defects in industrial circuits.