Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
A method for generating weighted random test pattern
IBM Journal of Research and Development
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Algorithms for current monitor based diagnosis of bridging and leakage faults
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A novel approach to delay-fault diagnosis
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
On improving fault diagnosis for synchronous sequential circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Design for manufacturability in submicron domain
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
On Dictionary-Based Fault Location in Digital Logic Circuits
IEEE Transactions on Computers
Location of Stuck-At Faults and Bridging Faults Based on Circuit Partitioning
IEEE Transactions on Computers
Diagnosis of Scan Cells in BIST Environment
IEEE Transactions on Computers
On the Adaptation of Viterbi Algorithm for Diagnosis of Multiple Bridging Faults
IEEE Transactions on Computers
Diagnosis Method Using ΔIDDQ Probabilistic Signatures: Theory and Results
Journal of Electronic Testing: Theory and Applications
A VHDL Fault Diagnosis Tool Using Functional Fault Models
IEEE Design & Test
Delay-Fault Diagnosis by Critical-Path Tracing
IEEE Design & Test
IDDQ Test and Diagnosis of CMOS Circuits
IEEE Design & Test
Automated Diagnosis in Testing and Failure Analysis
IEEE Design & Test
Modeling the Unmodelable: Algorithmic Fault Diagnosis
IEEE Design & Test
Poirot: Applications of a Logic Fault Diagnosis Tool
IEEE Design & Test
On applying non-classical defect models to automated diagnosis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Modeling the unknown! Towards model-independent fault and error diagnosis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Diagnosis method based on /spl Delta/Iddq probabilistic signatures: experimental results
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Fault diagnosis using state information
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
Voting model based diagnosis of bridging faults in combinational circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
An Improved Fault Diagnosis Algorithm Based on Path Tracing with Dynamic Circuit Extraction
ITC '00 Proceedings of the 2000 IEEE International Test Conference
POIROT1: A Logic Fault Diagnosis Tool and Its Applications
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Making Cause-Effect Cost Effective: Low-Resolution Fault Dictionaries
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Expediting Ramp-to-Volume Production
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Diagnostic Techniques for the IBM S/390 600 MHz G5 Microprocessor
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Correlation of Logical Failures to a Suspect Process Step
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Yield Analysis of Logic Circuits
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Understanding Yield Losses in Logic Circuits
IEEE Design & Test
Accurate Diagnosis of Multiple Faults
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
On per-test fault diagnosis using the X-fault model
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
An efficient method for improving the quality of per-test fault diagnosis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Multiple-fault diagnosis based on single-fault activation and single-output observation
Proceedings of the conference on Design, automation and test in Europe: Proceedings
An Efficient Dictionary Organization for Maximum Diagnosis
Journal of Electronic Testing: Theory and Applications
Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults
Journal of Electronic Testing: Theory and Applications
Improve the Quality of Per-Test Fault Diagnosis Using Output Information
Journal of Electronic Testing: Theory and Applications
Isolation of Failing Scan Cells through Convolutional Test Response Compaction
Journal of Electronic Testing: Theory and Applications
Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis
IEEE Transactions on Computers
Diagnosing at-speed scan BIST circuits using a low speed and low memory tester
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the conference on Design, automation and test in Europe
IEICE - Transactions on Information and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Adaptive Debug and Diagnosis Without Fault Dictionaries
Journal of Electronic Testing: Theory and Applications
Diagnosis of multiple-voltage design with bridge defect
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
S/390 G5 CMOS microprocessor diagnostics
IBM Journal of Research and Development
Diagnosis of integrated circuits with multiple defects of arbitrary characteristics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Techniques to prioritize paths for diagnosis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
BISD: scan-based built-in self-diagnosis
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Selection of a fault model for fault diagnosis based on unique responses
Proceedings of the Conference on Design, Automation and Test in Europe
A diagnosis algorithm for extreme space compaction
Proceedings of the Conference on Design, Automation and Test in Europe
An Effective and Accurate Methodology for the Cell Internal Defect Diagnosis
Journal of Electronic Testing: Theory and Applications
On undetectable faults and fault diagnosis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Selection of a fault model for fault diagnosis based on unique responses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Effective diagnostic pattern generation strategy for transition-delay faults in full-scan SOCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Diagnosis of single stuck-at faults and multiple timing faults in scan chains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improved diagnosis using enhanced fault dominance
Integration, the VLSI Journal
A Non-Enumerative Technique for Measuring Path Correlation in Digital Circuits
Journal of Electronic Testing: Theory and Applications
An ATE assisted DFD technique for volume diagnosis of scan chains
Proceedings of the 50th Annual Design Automation Conference
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The authors describe a method for diagnosing the failures observed in testing VLSI designs that use the scan-path structure. Diagnosis consists of simulating selected faults after testing using a fault simulator that allows the application of several patterns in parallel. The method is also suitable for signature-based random-pattern testing. The authors discuss diagnostic fault simulation, fault-list generation, relating faults to defects, diagnostic strategy, and random-pattern failures, and they report some experimental results to indicate the procedure's power.