Diagnosis and correction of logic design errors in digital circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Error diagnosis for transistor-level verification
DAC '94 Proceedings of the 31st annual Design Automation Conference
Multiple error diagnosis based on xlists
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Failure Diagnosis of Structured VLSI
IEEE Design & Test
Poirot: Applications of a Logic Fault Diagnosis Tool
IEEE Design & Test
Beyond the Byzantine Generals: Unexpected Behaviour and Bridging Fault Diagnosis
Proceedings of the IEEE International Test Conference on Test and Design Validity
Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis
Proceedings of the IEEE International Test Conference
Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm
Proceedings of the IEEE International Test Conference 2001
A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Full fault dictionary storage based on labeled tree encoding
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
A Technique for Logic Fault Diagnosis of Interconnect Open Defects
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Multiplets, Models, and the Search for Meaning: Improving Per-Test Fault Diagnosis
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Incremental Diagnosis of Multiple Open-Interconnects
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Fault Dictionary Size Reduction through Test Response Superposition
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
On Pass/Fail Dictionaries for Scan Circuits
ATS '01 Proceedings of the 10th Asian Test Symposium
Incremental Diagnosis and Correction of Multiple Faults and Errors
Proceedings of the conference on Design, automation and test in Europe
On Improving the Accuracy Of Multiple Defect Diagnosis
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Speeding Up The Byzantine Fault Diagnosis Using Symbolic Simulation
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Compact Dictionaries for Fault Diagnosis in Scan-BIST
IEEE Transactions on Computers
On per-test fault diagnosis using the X-fault model
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Bridge fault diagnosis using stuck-at fault simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On correction of multiple design errors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Fault diagnosis of full-scan designs has been progressed significantly. However, most existing techniques are aimed at a logic block with a single fault. Strategies on top of these block-level techniques are needed in order to successfully diagnose a large chip with multiple faults. In this paper, we present such a strategy. Our strategy is effective in identifying more than one fault accurately. It proceeds in two phases. In the first phase we concentrate on the identification of the so-called structurally independent faults based on a concept referred to as word-level prime candidate, while in the second phase we further trace the locations of the more elusive structural dependent faults. Experimental results show that this strategy is able to find 3 to 4 faults within 10 signal inspections for three real-life designs randomly injected with 5 node-type or stuck-at faults.