Failure Diagnosis of Structured VLSI
IEEE Design & Test
Beyond the Byzantine Generals: Unexpected Behaviour and Bridging Fault Diagnosis
Proceedings of the IEEE International Test Conference on Test and Design Validity
Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm
Proceedings of the IEEE International Test Conference 2001
Fault Diagnosis for Static CMOS Circuits
ATS '97 Proceedings of the 6th Asian Test Symposium
POIROT1: A Logic Fault Diagnosis Tool and Its Applications
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Multiplets, Models, and the Search for Meaning: Improving Per-Test Fault Diagnosis
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Speeding Up The Byzantine Fault Diagnosis Using Symbolic Simulation
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults
Journal of Electronic Testing: Theory and Applications
Improve the Quality of Per-Test Fault Diagnosis Using Output Information
Journal of Electronic Testing: Theory and Applications
A Method of Locating Open Faults on Incompletely Identified Pass/Fail Information
IEICE - Transactions on Information and Systems
IEICE - Transactions on Information and Systems
Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information
IEICE - Transactions on Information and Systems
Post-BIST Fault Diagnosis for Multiple Faults
IEICE - Transactions on Information and Systems
Parallel X-fault simulation with critical path tracing technique
Proceedings of the Conference on Design, Automation and Test in Europe
Design and analysis of compact dictionaries for diagnosis in scan-BIST
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This work proposes a new per-test fault diagnosis method based on the X-fault model. The X-fault model represents all possible behaviors of a physical defect or defects in a gate and/or on its fanout branches by using different X symbols on the fanout branches. A novel technique is proposed for analyzing the relation between observed and simulated responses to extract diagnostic information and to score the results of diagnosis. Experimental results show the effectiveness of our method.