Critical path tracing - an alternative to fault simulation
25 years of DAC Papers on Twenty-five years of electronic design automation
Differential fault simulation - a fast method using minimal memory
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Universal fault simulation using fault tuples
Proceedings of the 37th Annual Design Automation Conference
On the properties of the input pattern fault model
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Beyond the Byzantine Generals: Unexpected Behaviour and Bridging Fault Diagnosis
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Deterministic test generation for non-classical faults on the gate level
ATS '95 Proceedings of the 4th Asian Test Symposium
Test generation costs analysis and projections
DAC '80 Proceedings of the 17th Design Automation Conference
A Circuit Level Fault Model for Resistive Opens and Bridges
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Speeding Up The Byzantine Fault Diagnosis Using Symbolic Simulation
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
An Unified Fault Model and Test Generation Procedure for Interconnect Opens and Bridges
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
A Fast Algorithm for Critical Path Tracing in VLSI Digital Circuits
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
On per-test fault diagnosis using the X-fault model
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
A Deductive Method for Simulating Faults in Logic Circuits
IEEE Transactions on Computers
Modeling and Test Generation Algorithms for MOS Circuits
IEEE Transactions on Computers
The Region-Exhaustive Fault Model
ATS '07 Proceedings of the 16th Asian Test Symposium
Fast Bridging Fault Diagnosis using Logic Information
ATS '07 Proceedings of the 16th Asian Test Symposium
Parallel fault backtracing for calculation of fault coverage
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Adaptive Debug and Diagnosis without Fault Dictionaries
ETS '08 Proceedings of the 2008 13th European Test Symposium
IEICE - Transactions on Information and Systems
Diagnosis of Realistic Defects Based on the X-Fault Model
DDECS '08 Proceedings of the 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
SUPERB: Simulator utilizing parallel evaluation of resistive bridges
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Simulating Resistive-Bridging and Stuck-At Faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Finding the description of structure by counting method: a case study
SOFSEM'11 Proceedings of the 37th international conference on Current trends in theory and practice of computer science
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In this paper, a new very fast fault simulation method to handle the X-fault model is proposed. The method is based on a two-phase procedure. In the first phase, a parallel exact critical path fault tracing is used to determine all the detected stuck-at faults in the circuit, and in the second phase a postprocess is launched which will determine the detectability of X-faults.