Universal fault simulation using fault tuples

Authors:
Kumar N. Dwarakanath;R. D. Blanton
Affiliations:
Center for Electronic Design Automation, Carnegie Mellon University, Pittsburgh, PA;Center for Electronic Design Automation, Carnegie Mellon University, Pittsburgh, PA
Venue:
Proceedings of the 37th Annual Design Automation Conference
Year:
2000

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Abstract

We introduce a new fault representation mechanism for digital circuits based on fault tuples. A fault tuple is a simple 3-element condition for a signal line, its value, and clock cycle constrain t. AND-OR expressions of fault tuples are used to represent arbitrary misbehaviors. A fault simulator based on fault tuples was used to conduct experiments on benc hmark circuits. Simulation results show that a 17% reduction of average CPU time is achiev ed when performing sim ulation on all fault types simultaneously, as opposed to individually. We expect further improvements in speedup when the shared characteristics of the various fault types are better exploited.