Synthesis of Delay-Verifiable Combinational Circuits
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Generation of High Quality Tests for Robustly Untestable Path Delay Faults
IEEE Transactions on Computers
Deriving Logic Systems for Path Delay Test Generation
IEEE Transactions on Computers
Universal fault simulation using fault tuples
Proceedings of the 37th Annual Design Automation Conference
Introduction to Digital Logic Design
Introduction to Digital Logic Design
Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Universal Test Generation Using Fault Tuples
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Delay Testing of SOI Circuits: Challenges with the History Effect
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Fault tuples: theory and applications
Fault tuples: theory and applications
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Fault tuples have introduced a fault model independentmethodology for digital circuit test analysis.However,the {0, 1, X} algebra currently used with faulttuples allows only one form of path sensitization.Thesensitization options for fault tuples is enhanced basedon a 5-value algebra.The 5-value algebra enablesa more detailed test analysis through the selection ofone of three types of sensitization.Simulation experimentsperformed using the ITC'99 benchmark circuitsfor transition and path delay faults reveal that faultscan be simultaneously analyzed under different types ofsensitization criteria with little increase in memory andCPU time.