DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Classification and Test Generation for Path-Delay FaultsUsing Single Struck-at Fault Tests
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Universal fault simulation using fault tuples
Proceedings of the 37th Annual Design Automation Conference
An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Test generation in VLSI circuits for crosstalk noise
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Simulation of non-classical Faults on the Gate Level - The Fault Simulator COMISM -
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
The Stuck-At Fault: It Ain't Over 'Til It's Over
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Stuck-At Fault: A Fault Model for the Next Millennium
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Properties of the input pattern fault model
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
IEEE Transactions on Computers
Diagnosis of automata failures: a calculus and a method
IBM Journal of Research and Development
Testing for faults in combinational cellular logic arrays
FOCS '67 Proceedings of the 8th Annual Symposium on Switching and Automata Theory (SWAT 1967)
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Locating bridging faults using dynamically computed stuck-at fault dictionaries
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Identification of Crosstalk Switch Failures in Domino CMOS Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Generalized Sensitization using Fault Tuples
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Multiple-detect ATPG based on physical neighborhoods
Proceedings of the 43rd annual Design Automation Conference
| Hi-index | 0.00 |
A test generation tool for combinational circuitscalled FATGEN has been developed based on the notionof fault tuples. FATGEN can be used to simultaneouslygenerate tests for many types of misbehavior that occurin digital systems. Individual experiments involvingSSL, transistor stuck-open, path delay and bridgingfaults for the ISCAS85 benchmark circuits reveal anaverage speedup of nearly 32% and test set compactionof 60% when faults of all types are analyzed simultaneously.In addition, there is an average reduction ofapproximately 34% in the number of aborted faults.