A programming language
Uncertainty, Energy, and Multiple-Valued Logics
IEEE Transactions on Computers
Minimization by the D Algorithm
IEEE Transactions on Computers
MOS test pattern generation using path algebras
IEEE Transactions on Computers
A comprehensive approach to the partial scan problem using implicit state enumeration
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Training diploma students on ATE-related module
ATS '95 Proceedings of the 4th Asian Test Symposium
A Fault-Independent Transitive Closure Algorithm for Redundancy Identification
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
16.2 A Structural Approach for Space Compaction for Concurrent Checking and BIST
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Universal Test Generation Using Fault Tuples
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Conversion of Small Functional Test Sets of Nonscan Blocks to Scan Patterns
ITC '00 Proceedings of the 2000 IEEE International Test Conference
STAR-ATPG: A High Speed Test Pattern Generator for Large Scan Designs
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An effective and efficient ATPG-based combinational equivalence checker
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic
IEEE Transactions on Computers
Design for Testability A Survey
IEEE Transactions on Computers
Algebraic Fault Analysis for Constrained Combinational Networks
IEEE Transactions on Computers
Diagnosis of Single-Gate Failures in Combinational circuits
IEEE Transactions on Computers
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
An Experimental Delay Test Generator for LSI Logic
IEEE Transactions on Computers
An Approach to the Diagnosis of Intermittent Faults
IEEE Transactions on Computers
Fault Masking in Combinational Logic Circuits
IEEE Transactions on Computers
Diversified Test Methods for Local Control Units
IEEE Transactions on Computers
Optimal Detection of Bridge Faults and Stuck-At Faults in Two-Level Logic
IEEE Transactions on Computers
Path Complexity of Logic Networks
IEEE Transactions on Computers
Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis
IEEE Transactions on Computers
The Complexity of Fault Detection Problems for Combinational Logic Circuits
IEEE Transactions on Computers
Fault-Tolerant Computing: A Introduction
IEEE Transactions on Computers
Processor Testability and Design Consequences
IEEE Transactions on Computers
A Heuristic Algorithm for the Testing of Asynchronous Circuits
IEEE Transactions on Computers
The Weighted Random Test-Pattern Generator
IEEE Transactions on Computers
An Algorithm for the Generation of Test Sets for Combinational Logic Networks
IEEE Transactions on Computers
Minimal Redundant Logic for High Reliability and Irredundant Testability
IEEE Transactions on Computers
A Hierarchical, Path-Oriented Approach to Fault Diagnosis in Modular Combinational Circuits
IEEE Transactions on Computers
Test Generation Algorithms for Computer Hardware Description Languages
IEEE Transactions on Computers
Computer-Aided Test Generation for Four-Phase MOS LSI Circuits
IEEE Transactions on Computers
Minimal Fault Tests for Redundant Combinational Networks
IEEE Transactions on Computers
Functional Partitioning and Simulation of Digital Circuits
IEEE Transactions on Computers
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
Detection of Single, Stuck-Type Failures in Multivalued Combinational Networks
IEEE Transactions on Computers
IEEE Transactions on Computers
Verification Techniques for System-Level Design
Verification Techniques for System-Level Design
Circuit Structure and Switching Function Verification
IEEE Transactions on Computers
Solution of systems of Boolean equations via the integer domain
Information Sciences: an International Journal
Threshold testing: improving yield for nanoscale VLSI
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal of Electronic Testing: Theory and Applications
Initialization-based test pattern generation for asynchronous circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computational complexity in logic testing
INES'10 Proceedings of the 14th international conference on Intelligent engineering systems
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Development of tests for VLSI circuit testability at the upper design levels
Automation and Remote Control
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Design of an efficient weighteld random pattern generation system
ITC'94 Proceedings of the 1994 international conference on Test
Behavioral test generation using mixed integer non-linear programming
ITC'94 Proceedings of the 1994 international conference on Test
B-algorithm: a behavioral test generation algorithm
ITC'94 Proceedings of the 1994 international conference on Test
Optimal logic synthesis and testability: two faces of the same coin
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Fault isolation in grey systems
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
A method to generate tests for combinational logic circuits using an ultrahigh-speed logic simulator
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Hierarchical test generation using precomputed tests for modules
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
The KARL/KARATE system - automatic test pattern generation based on RT level descriptions
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Reconfigurable hardware for Pseudo-exhaustive test
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
G-RIDDLE: a formal analysis of logic designs conducive to the acceleration of backtracing
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Delay test generation 2: algebra and algorithms
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Design of fault-tolerant computers
FTCS'95 Proceedings of the Twenty-Fifth international conference on Fault-tolerant computing
A novel automatic test pattern generator for asynchronous sequential digital circuits
Microelectronics Journal
Automatic test pattern generation for asynchronous networks
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Test generation for MOS circuits
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
LSI logic testing: an overview
IEEE Transactions on Computers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic test pattern generation with BOA
PPSN'06 Proceedings of the 9th international conference on Parallel Problem Solving from Nature
Model-Based monitoring and diagnosis chip for embedded systems
AIMSA'06 Proceedings of the 12th international conference on Artificial Intelligence: methodology, Systems, and Applications
Time complexity of decision trees
Transactions on Rough Sets III
Automatic test pattern generation
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Formal Verification and Diagnosis of Combinational Circuit Designs with Propositional Logic
Fundamenta Informaticae
Accurate QBF-based test pattern generation in presence of unknown values
Proceedings of the Conference on Design, Automation and Test in Europe
GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
| Hi-index | 0.10 |
The problem considered is the diagnosis of failures of automata, specifically, failures that manifest themselves as logical malfunctions. A review of previous methods and results is first given. A method termed the "calculus of D-cubes" is then introduced, which allows one to describe and compute the behavior of failing acyclic automata, both internally and externally. An algorithm, called the D-algorithm, is then developed which utilizes this calculus to compute tests to detect failures. First a manual method is presented, by means of an example. Thence, the D-algorithm is precisely described by means of a program written in Iverson notation. Finally, it is shown for the acyclic case in which the automaton is constructed from AND'S, NAND'S, OR'S and NOR'S that if a test exists, the D-algorithm will compute such a test.