Test generation for MOS circuits

Authors:
Harry H. Chen;Robert G. Mathews;John A. Newkirk
Affiliations:
Information Systems Laboratory, Stanford University, Stanford, CA;Information Systems Laboratory, Stanford University, Stanford, CA;Information Systems Laboratory, Stanford University, Stanford, CA
Venue:
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Year:
1984

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Abstract

Test generation for transistor switch faults is considered for nMOS combinational circuits. Examination of fault effects shows that memory and non-digital signals can result. A test strategy that accounts for MOS physical properties such as charge storage and bidirectionality is developed. Abstraction of physical effects using ternary algebra can guarantee the generation of valid tests.