Computer Logic, Testing and Verification
Computer Logic, Testing and Verification
A SWITCH-LEVEL SIMULATION MODEL FOR INTEGRATED LOGIC CIRCUITS
A SWITCH-LEVEL SIMULATION MODEL FOR INTEGRATED LOGIC CIRCUITS
VHDL switch level fault simulation
EURO-DAC '94 Proceedings of the conference on European design automation
Delay modeling and time of bipolar digital circuits
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Performance evaluation of FMOSSIM, a concurrent switch-level fault simulator
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Test generation for MOS circuits
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
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In this paper we introduce the concept of implication for MOS switch level circuits. The implication performed on these circuits is an extension of the classical implication now applied to Boolean logic networks. Given the ability to perform implication on MOS circuits we can then; generate functional macromodels of MOS circuits, use these macromodels to verify the Boolean function realized by the MOS circuit extracted from the mask set, generate, directly from the MOS circuit sets of tests for nodes stuck-at-1 and stuck-at-0 as well as transistors stuck open and stuck short. We present the conceptual frame work and algorithms for performing implication on MOS networks. We present examples of MOS implication and discuss extensions of the algorithm to test generation, and to a first order instead of zero order MOS network.