An object-oriented swicth-level simulator
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A transistor-level logic-with-timing simulator for MOS circuits
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Hierarchical VLSI design systems based on attribute grammars
POPL '86 Proceedings of the 13th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Implication algorithms for MOS switch level functional macromodeling implication and testing
DAC '82 Proceedings of the 19th Design Automation Conference
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The switch-level model describes the logical behavior of digital integrated circuits implemented in metal oxide semiconductors (MOS) technology. A network in this model consists of a set of nodes connected by transistor "switches." Many aspects of MOS circuits can be described which cannot be expressed in the Boolean logic gate model, such as bidirectional pass transistors, dynamic storage, and charge sharing. Furthermore, the logic network can be extracted directly from the mask specification of a circuit by a relatively straightforward computer program. Unlike analog circuit models, however, the nodes in a switch-level network assume discrete logic states 0, 1, and X (for unknown), and the transistors assume discrete states "open," "closed," and "unknown." This model can form the basis of a logic simulator for MOS circuits with performance comparable to logic gate simulators. This dissertation presents a rigorous development of the switch-level model and several simulation algorithms.