Roving Emulation as a Fault Detection Mechanism
IEEE Transactions on Computers
On the Use of "Importance Weights" in Assessing Subsystem Reliability
IEEE Transactions on Computers
SCIRTSS: A Search System for Sequential Circuit Test Sequences
IEEE Transactions on Computers
Efficiency of Random Compact Testing
IEEE Transactions on Computers
The Error Latency of a Fault in a Sequential Digital Circuit
IEEE Transactions on Computers
Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic Networks
IEEE Transactions on Computers
The Weighted Random Test-Pattern Generator
IEEE Transactions on Computers
An Algorithm for the Generation of Test Sets for Combinational Logic Networks
IEEE Transactions on Computers
Algebraic Properties of Functions Affecting Optimum Fault-Tolerant Realizations
IEEE Transactions on Computers
Procedures for increasing fault coverage for digital networks
AFIPS '72 (Fall, part I) Proceedings of the December 5-7, 1972, fall joint computer conference, part I
An analysis of the multiple fault detection capabilities of single stuck-at fault test sets
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Test generation for MOS circuits
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
An automatic test generation system for illiac IV logic boards
IEEE Transactions on Computers
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Programmed algorithms for test generation and test evaluation are described. The D-notation is introduced and a test generator (DALG) for combinational logic is presented. The sequential case is then examined. "Real life" constraints related to LSI testing are discussed. Two heuristic test generators satisfying these constraints are introduced. The iterative test generator (ITG) generates tests by transforming the given sequential circuit into an iterative combinational circuit. The macroblock test generator (MTG) uses the same approach but makes use of complex primitives (latches, triggers, etc.) to represent the circuit to be tested. Both the ITG and the MTG are not always guaranteed to generate good tests for each examined failure, and are used in connection with a test evaluator (simulator). Basic features of this evaluator are discussed.